Polysilicon is widely used to form gate electrodes of metal-oxide-semiconductor (MOS) devices. Polysilicon has a high resistivity, and hence needs to be doped, so that its resistivity may satisfy the requirement of the MOS devices. The doped impurity is activated through anneals.
MOS devices with polysilicon gate electrodes exhibit a carrier depletion effect, which is also referred to as a poly depletion effect. The poly depletion effect occurs when applied electrical fields sweep away carriers from regions close to gate dielectrics, forming depletion layers. In an n-doped polysilicon layer, the depletion layer includes ionized non-mobile donor sites, whereas in a p-doped polysilicon layer, the depletion layer includes ionized non-mobile acceptor sites. The depletion effect results in an increase in the effective gate dielectric thickness, making it more difficult for an inversion layer to be created at the surface of the semiconductor.
In order to reduce the poly depletion effect, either the impurity dosage or the temperature of annealing, which is used to activate the impurity, needs to be increased. However, these approaches may adversely result in the dopants to be diffused into gate dielectrics, causing the degradation of the reliability of gate dielectrics and the increase in the gate leakage currents. Further, the dopants may penetrate through the gate dielectrics and diffuse into the underlying substrates, causing the threshold voltages of the resulting MOS devices to be increased.
With the increasing down-scaling of integrated circuits, gate dielectrics also become thinner, making the situation worse. The leakage currents tend to increase with the reduction in the thicknesses of gate dielectrics. This makes the penetration of dopants through gate dielectrics even easier. New methods to reduce the diffusion effect are thus needed.